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| MCP3221 Low Power 12-Bit A/D Converter With I2CTM Interface Features * * * * * 12-bit resolution 1 LSB DNL, 2 LSB INL max. 250 A max conversion current 5 nA typical standby current, 1 A max. I2CTM-compatible serial interface - 100 kHz I2C Standard Mode - 400 kHz I2C Fast Mode Up to 8 devices on a single 2-Wire bus 22.3 ksps in I2C Fast Mode Single-ended analog input channel On-chip sample and hold On-chip conversion clock Single-supply specified operation: 2.7V to 5.5V Temperature range: - Industrial: -40C to +85C - Extended: -40C to +125C Small SOT-23-5 package Description The Microchip Technology Inc. MCP3221 is a successive approximation A/D converter with 12-bit resolution. Available in the SOT-23-5 package, this device provides one single-ended input with very low power consumption. Based on an advanced CMOS technology, the MCP3221 provides a low maximum conversion current and standby current of 250 A and 1 A, respectively. Low current consumption, combined with the small SOT-23 package, make this device ideal for battery-powered and remote data acquisition applications. Communication to the MCP3221 is performed using a 2-wire, I2C compatible interface. Standard (100 kHz) and Fast (400 kHz) I2C modes are available with the device. An on-chip conversion clock enables independent timing for the I2C and conversion clocks. The device is also addressable, allowing up to eight devices on a single 2-wire bus. The MCP3221 runs on a single supply voltage that operates over a broad range of 2.7V to 5.5V. This device also provides excellent linearity of 1 LSB differential non-linearity and 2 LSB integral non-linearity, maximum. * * * * * * * * Applications * * * * * Data Logging Multi-zone Monitoring Hand-Held Portable Applications Battery-Powered Test Equipment Remote or Isolated Data Acquisition Functional Block Diagram VDD VSS Package Type 5-Pin SOT-23 SCL Sample and Hold Clock Control Logic AIN 3 4 SDA SCL SDA I2CTM Interface DAC Comparator 12-bit SAR - + VDD 1 VSS 2 5 MCP3221 AIN (c) 2006 Microchip Technology Inc. DS21732C-page 1 MCP3221 1.0 ELECTRICAL CHARACTERISTICS Stresses above those listed under "Maximum ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings VDD...................................................................................7.0V Analog input pin w.r.t. VSS .......... ............. -0.6V to VDD +0.6V SDA and SCL pins w.r.t. VSS........... .........-0.6V to VDD +1.0V Storage temperature .....................................-65C to +150C Ambient temp. with power applied ................-65C to +125C Maximum Junction Temperature .......... .........................150C ESD protection on all pins (HBM) ................................. 4 kV DC ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5.0V, VSS = GND, RPU = 2 k TAMB = -40C to +85C, I2C Fast Mode Timing: fSCL = 400 kHz (Note 3). Parameters DC Accuracy Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Dynamic Performance Total Harmonic Distortion Signal-to-Noise and Distortion Spurious-Free Dynamic Range Analog Input Input Voltage Range Leakage Current SDA/SCL (open-drain output): Data Coding Format High-level input voltage Low-level input voltage Low-level output voltage Hysteresis of Schmitt trigger inputs Input leakage current Output leakage current Pin capacitance (all inputs/outputs) Bus Capacitance Note 1: 2: 3: 4: 5: VIH VIL VOL VHYST ILI ILO CIN, COUT CB -- -- -- -1 -1 -- -- Straight Binary 0.7 VDD -- -- -- 0.05 VDD -- -- -- -- -- 0.3 VDD 0.4 -- +1 +1 10 400 V V V V A A pF pF IOL = 3 mA, RPU = 1.53 k fSCL = 400 kHz only VIN = 0.1 VDD and 0.9 VDD VOUT = 0.1 VSS and 0.9 VDD TAMB = 25C, f = 1 MHz; (Note 2) SDA drive low, 0.4V VSS-0.3 -1 -- -- VDD+0.3 +1 V A 2.7V VDD 5.5V THD SINAD SFDR -- -- -- -82 72 86 -- -- -- dB dB dB VIN = 0.1V to 4.9V @ 1 kHz VIN = 0.1V to 4.9V @ 1 kHz VIN = 0.1V to 4.9V @ 1 kHz INL DNL -- -- -- -- 12 0.75 0.5 0.75 -1 2 1 2 3 bits LSB LSB LSB LSB No missing codes Sym Min Typ Max Units Conditions "Sample time" is the time between conversions once the address byte has been sent to the converter. Refer to Figure 5-6. This parameter is periodically sampled and not 100% tested. RPU = Pull-up resistor on SDA and SCL. SDA and SCL = VSS to VDD at 400 kHz. tACQ and tCONV are dependent on internal oscillator timing. See Figure 5-5 and Figure 5-6 for relation to SCL. DS21732C-page 2 (c) 2006 Microchip Technology Inc. MCP3221 DC ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5.0V, VSS = GND, RPU = 2 k TAMB = -40C to +85C, I2C Fast Mode Timing: fSCL = 400 kHz (Note 3). Parameters Power Requirements Operating Voltage Conversion Current Standby Current Active bus current Conversion Rate Conversion Time Analog Input Acquisition Time Sample Rate Note 1: 2: 3: 4: 5: tCONV tACQ fSAMP -- -- -- 8.96 1.12 -- -- -- 22.3 s s ksps Note 5 Note 5 fSCL = 400 kHz (Note 1) VDD IDD IDDS IDDA 2.7 -- -- -- -- 175 0.005 -- 5.5 250 1 120 V A A A SDA, SCL = VDD Note 4 Sym Min Typ Max Units Conditions "Sample time" is the time between conversions once the address byte has been sent to the converter. Refer to Figure 5-6. This parameter is periodically sampled and not 100% tested. RPU = Pull-up resistor on SDA and SCL. SDA and SCL = VSS to VDD at 400 kHz. tACQ and tCONV are dependent on internal oscillator timing. See Figure 5-5 and Figure 5-6 for relation to SCL. TEMPERATURE SPECIFICATIONS Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5.0V, VSS = GND. Parameters Temperature Ranges Industrial Temperature Range Extended Temperature Range Operating Temperature Range Storage Temperature Range Thermal Package Resistances Thermal Resistance, 5L-SOT23 JA -- 256 -- C/W TA TA TA TA -40 -40 -40 -65 -- -- -- -- +85 +125 +125 +150 C C C C Symbol Min Typ Max Units Conditions (c) 2006 Microchip Technology Inc. DS21732C-page 3 MCP3221 TIMING SPECIFICATIONS Electrical Characteristics: All parameters apply at VDD = 2.7V - 5.5V, VSS = GND, TAMB = -40C to +85C. Parameters I2 C Standard Mode fSCL THIGH TLOW TR TF THD:STA TSU:STA TSU:DAT TSU:STO THD:STD TAA TBUF TSP FSCL THIGH TLOW TR TF THD:STA TSU:STA THD:DAT TSU:DAT TSU:STO THD:STD TAA TBUF TSP 0 4000 4700 -- -- 4000 4700 250 4000 4000 -- 4700 -- 0 600 1300 20 + 0.1CB 20 + 0.1CB 600 600 0 100 600 600 -- 1300 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 100 -- -- 1000 300 -- -- -- -- -- 3500 -- 50 400 -- -- 300 300 -- -- 0.9 -- -- -- 900 -- 50 kHz ns ns ns ns ns ns ns ns ns ns ns ns kHz ns ns ns ns ns ns ms ns ns ns ns ns ns Note 2 SDA and SCL pins (Note 1) From VIL to VIH (Note 1) From VIL to VIH (Note 1) Note 2 SDA and SCL pins (Note 1) From VIL to VIH (Note 1) From VIL to VIH (Note 1) Sym Min Typ Max Units Conditions Clock frequency Clock high time Clock low time SDA and SCL rise time SDA and SCL fall time START condition hold time START condition setup time Data input setup time STOP condition setup time STOP condition hold time Output valid from clock Bus free time Input filter spike suppression I2C Fast Mode Clock frequency Clock high time Clock low time SDA and SCL rise time SDA and SCL fall time START condition hold time START condition setup time Data input hold time Data input setup time STOP condition setup time STOP condition hold time Output valid from clock Bus free time Input filter spike suppression Note 1: 2: This parameter is periodically sampled and not 100% tested. Time the bus must be free before a new transmission can start. TF SCL SDA IN TSU:STA TLOW TSP THD:STA THIGH VHYS TR THD:DAT TSU:DAT TSU:STO SDA OUT TAA TBUF FIGURE 1-1: Standard and Fast Mode Bus Timing Data. DS21732C-page 4 (c) 2006 Microchip Technology Inc. MCP3221 2.0 Note: TYPICAL PERFORMANCE CURVES The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion Mode (fSAMP = 22.3 ksps), TA = +25C. 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 100 Positive INL INL (LSB) Negative INL INL (LSB) Positive INL Negative INL 100 200 300 I2C Bus Rate (kHz) 400 200 I2C Bus Rate (kHz) 300 400 FIGURE 2-1: INL vs. Clock Rate. FIGURE 2-4: (VDD = 2.7V). 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 2.5 3 INL vs. Clock Rate 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 2.5 3 Positive INL INL (LSB) Negative INL INL (LSB) Positive INL Negative INL 3.5 4 VDD (V) 4.5 5 5.5 3.5 4 VDD (V) 4.5 5 5.5 FIGURE 2-2: INL vs. VDD - I2CTM Standard Mode (fSCL = 100 kHz). 2 1.5 1 FIGURE 2-5: INL vs. VDD - I2CTM Fast Mode (fSCL = 400 kHz). 2 1.5 1 INL (LSB) 0.5 0 -0.5 -1 -1.5 -2 INL (LSB) 0.5 0 -0.5 -1 -1.5 -2 0 1024 2048 Digital Code 3072 4096 0 1024 2048 Digital Code 3072 4096 FIGURE 2-3: INL vs. Code (Representative Part). FIGURE 2-6: INL vs. Code (Representative Part, VDD = 2.7V). (c) 2006 Microchip Technology Inc. DS21732C-page 5 MCP3221 Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion Mode (fSAMP = 22.3 ksps), TA = +25C. 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 -50 -25 0 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 -50 -25 0 Positive INL Positive INL INL (LSB) Negative INL INL (LSB) Negative INL 25 50 75 100 125 25 50 75 100 125 Temperature (C) Temperature (C) FIGURE 2-7: INL vs. Temperature. FIGURE 2-10: (VDD = 2.7V). 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 100 INL vs. Temperature 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 100 DNL (LSB) Positive DNL DNL (LSB) Positive DNL Negative DNL Negative DNL 200 I C Bus Rate (kHz) 2 300 400 200 I C Bus Rate (kHz) 2 300 400 FIGURE 2-8: DNL vs. Clock Rate. FIGURE 2-11: (VDD = 2.7V). 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 2.5 3 DNL vs. Clock Rate 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 2.5 3 DNL (LSB) Positive DNL Positive DNL Negative DNL DNL (LSB) Negative DNL 3.5 4 VDD (V) 4.5 5 5.5 3.5 4 VDD (V) 4.5 5 5.5 FIGURE 2-9: DNL vs. VDD - I2CTM Standard Mode (fSCL = 100 kHz). FIGURE 2-12: DNL vs. VDD - I2CTM Fast Mode (fSCL = 400 kHz). DS21732C-page 6 (c) 2006 Microchip Technology Inc. MCP3221 Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion Mode (fSAMP = 22.3 ksps), TA = +25C. 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 1024 2048 Digital Code 3072 4096 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 0 1024 2048 Digital Code 3072 4096 DNL (LSB) FIGURE 2-13: DNL vs. Code (Representative Part). 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 -50 -25 0 FIGURE 2-16: DNL vs. Code (Representative Part, VDD = 2.7V). 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 -50 -25 0 DNL (LSB) DNL (LSB) DNL (LSB) Positive DNL Positive DNL Negative DNL Negative DNL 25 50 75 100 125 25 50 75 100 125 Temperature (C) Temperature (C) FIGURE 2-14: DNL vs. Temperature. FIGURE 2-17: (VDD = 2.7V). 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 2.5 3 DNL vs. Temperature 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 -0.9 -1 2.5 fSCL = 100 kHz & 400 kHz Fast Mode (fSCL= 100 kHz) Standard Mode (fSCL= 400 kHz) 3 3.5 4 VDD (V) 4.5 5 5.5 Offset Error (LSB) Gain Error (LSB) 3.5 4 VDD (V) 4.5 5 5.5 FIGURE 2-15: Gain Error vs. VDD. FIGURE 2-18: Offset Error vs. VDD. (c) 2006 Microchip Technology Inc. DS21732C-page 7 MCP3221 Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion Mode (fSAMP = 22.3 ksps), TA = +25C. 3 Offset Error (LSB) 2 Gain Error (LSB) 1 0 -1 -2 -3 -50 VDD = 5V VDD = 2.7V 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -50 VDD = 5V VDD = 2.7V -25 0 25 50 75 100 125 -25 0 25 50 75 100 125 Temperature (C) Temperature (C) FIGURE 2-19: Gain Error vs. Temperature. FIGURE 2-22: Temperature. 100 90 80 70 60 50 40 30 20 10 0 1 Offset Error vs. 100 90 80 70 60 50 40 30 20 10 0 1 VDD = 5V VDD = 5V VDD = 2.7V SINAD (dB) SNR (dB) VDD = 2.7V 10 Input Frequency (kHz) 10 Input Frequency (kHz) FIGURE 2-20: 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 1 SNR vs. Input Frequency. FIGURE 2-23: 80 70 60 SINAD (dB) 50 40 30 20 10 0 SINAD vs. Input Frequency. VDD = 5V THD (dB) VDD = 5V VDD = 2.7V VDD = 2.7V 10 Input Frequency (kHz) -40 -30 -20 -10 0 Input Signal Level (dB) FIGURE 2-21: THD vs. Input Frequency. FIGURE 2-24: Level. SINAD vs. Input Signal DS21732C-page 8 (c) 2006 Microchip Technology Inc. MCP3221 Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion Mode (fSAMP = 22.3 ksps), TA = +25C. 12 11.95 11.9 11.85 11.8 11.75 11.7 11.65 11.6 11.55 11.5 2.5 3 3.5 4 VDD (V) 4.5 5 5.5 12 11.5 ENOB (rms) 11 10.5 10 9.5 9 1 Input Frequency (kHz) 10 VDD = 2.7V VDD = 5V ENOB (rms) FIGURE 2-25: 100 90 80 70 60 50 40 30 20 10 0 1 ENOB vs. VDD. FIGURE 2-28: ENOB vs. Input Frequency. VDD = 5V 10 -10 Amplitude (dB) fSAMP = 5.6 ksps SFDR (dB) -30 -50 -70 -90 -110 -130 0 500 1000 1500 2000 2500 VDD = 2.7V 10 Input Frequency (kHz) Frequency (Hz) FIGURE 2-26: SFDR vs. Input Frequency. FIGURE 2-29: Spectrum Using I2CTM Standard Mode (Representative Part, 1 kHz Input Frequency). 250 200 IDD (A) 150 100 50 0 10 -10 Amplitude (dB) -30 -50 -70 -90 -110 -130 0 2000 4000 6000 8000 10000 Frequency (Hz) 2.5 3 3.5 4 VDD (V) 4.5 5 5.5 FIGURE 2-27: Spectrum Using I2CTM Fast Mode (Representative Part, 1 kHz Input Frequency). FIGURE 2-30: IDD (Conversion) vs. VDD. (c) 2006 Microchip Technology Inc. DS21732C-page 9 MCP3221 Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion Mode (fSAMP = 22.3 ksps), TA = +25C. 200 180 160 140 120 100 80 60 40 20 0 0 100 90 80 70 60 50 40 30 20 10 0 0 100 VDD = 5V IDDA (A) IDD (A) VDD = 5V VDD = 2.7V VDD = 2.7V 100 200 300 2 I C Clock Rate (kHz) 400 200 300 2 I C Clock Rate (kHz) 400 FIGURE 2-31: Rate. 250 200 IDD (A) 150 100 50 0 -50 -25 0 IDD (Conversion) vs. Clock FIGURE 2-34: Rate. 100 90 80 70 60 50 40 30 20 10 0 -50 -25 0 IDDA (Active Bus) vs. Clock VDD = 5V VDD = 5V VDD = 2.7V IDDA (A) VDD = 2.7V 25 50 75 100 125 25 50 75 100 125 Temperature (C) Temperature (C) FIGURE 2-32: Temperature. 100 90 80 70 60 50 40 30 20 10 0 2.5 3 IDD (Conversion) vs. FIGURE 2-35: Temperature. 60 50 IDDS (pA) 40 30 20 10 0 IDDA (Active Bus) vs. IDDA (A) 3.5 4 VDD (V) 4.5 5 5.5 2.5 3 3.5 4 VDD (V) 4.5 5 5.5 FIGURE 2-33: IDDA (Active Bus) vs. VDD. FIGURE 2-36: IDDS (Standby) vs. VDD. DS21732C-page 10 (c) 2006 Microchip Technology Inc. MCP3221 Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, I2C Fast Mode Timing (SCL = 400 kHz), Continuous Conversion Mode (fSAMP = 22.3 ksps), TA = +25C. 2.1 1000 100 10 IDDS (nA) 1 0.1 0.01 0.001 0.0001 -50 -25 0 25 50 75 100 125 Temperature (C) Test Circuits VDD = 5V 10 F 0.1 F 2 k 2 k VDDSDA MCP3221 VSS SCL AIN VIN FIGURE 2-37: Temperature. 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 -50 -25 0 IDDS (Standby) vs. VCM = 2.5V Analog Input Leakage (nA) FIGURE 2-39: Typical Test Configuration. 25 50 75 100 125 Temperature (C) FIGURE 2-38: Temperature. Analog Input Leakage vs. (c) 2006 Microchip Technology Inc. DS21732C-page 11 MCP3221 3.0 PIN FUNCTIONS PIN FUNCTION TABLE Function +2.7V to 5.5V Power Supply Ground Analog Input Serial Data In/Out Serial Clock In Name VDD VSS AIN SDA SCL 3.3 Serial Data (SDA) TABLE 3-1: SDA is a bidirectional pin used to transfer addresses and data into and out of the device. Since it is an opendrain terminal, the SDA bus requires a pull-up resistor to VDD (typically 10 k for 100 kHz and 2 k for 400 kHz SCL clock speeds). Refer to Section 6.2 "Connecting to the I2C Bus", "Connecting to the I2C Bus", for more information. For normal data transfer, SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the START and STOP conditions. Refer to Section 5.1 "I2C Bus Characteristics", "I2C Bus Characteristics". 3.1 VDD and VSS The VDD pin, with respect to VSS, provides power to the device as well as a voltage reference for the conversion process. Refer to Section 6.4 "Device Power and Layout Considerations", "Device Power and Layout Considerations", for tips on power and grounding. 3.4 Serial Clock (SCL) 3.2 Analog Input (AIN) AIN is the input pin to the sample-and-hold circuitry of the Successive Approximation Register (SAR) converter. Care should be taken in driving this pin. Refer to Section 6.1 "Driving the Analog Input", "Driving the Analog Input". For proper conversions, the voltage on this pin can vary from VSS to VDD. SCL is an input pin used to synchronize the data transfer to and from the device on the SDA pin and is an open-drain terminal. Therefore, the SCL bus requires a pull-up resistor to VDD (typically 10 k for 100 kHz and 2 k for 400 kHz SCL clock speeds. Refer to Section 6.2 "Connecting to the I2C Bus", "Connecting to the I2C Bus"). For normal data transfer, SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the START and STOP conditions. Refer to Section 6.1 "Driving the Analog Input", "Driving the Analog Input". DS21732C-page 12 (c) 2006 Microchip Technology Inc. MCP3221 4.0 DEVICE OPERATION 4.2 Conversion Time (tCONV) The MCP3221 employs a classic SAR architecture. This architecture uses an internal sample and hold capacitor to store the analog input while the conversion is taking place. At the end of the acquisition time, the input switch of the converter opens and the device uses the collected charge on the internal sample-and-hold capacitor to produce a serial 12-bit digital output code. The acquisition time and conversion is self-timed using an internal clock. After each conversion, the results are stored in a 12-bit register that can be read at any time. Communication with the device is accomplished with a 2-wire, I2C interface. Maximum sample rates of 22.3 ksps are possible with the MCP3221 in a continuous-conversion mode and an SCL clock rate of 400 kHz. The conversion time is the time required to obtain the digital result once the analog input is disconnected from the holding capacitor. With the MCP3221, the specified conversion time is typically 8.96 s. This time is dependent on the internal oscillator and is independent of SCL. 4.3 Acquisition Time (tACQ) The acquisition time is the amount of time the sample cap array is acquiring charge. The acquisition time is, typically, 1.12 s. This time is dependent on the internal oscillator and independent of SCL. 4.4 Sample Rate 4.1 Digital Output Code The digital output code produced by the MCP3221 is a function of the input signal and power supply voltage, VDD. As the VDD level is reduced, the LSB size is reduced accordingly. The theoretical LSB size is shown below. Sample rate is the inverse of the maximum amount of time that is required from the point of acquisition of the first conversion to the point of acquisition of the second conversion. The sample rate can be measured either by single or continuous conversions. A single conversion includes a Start Bit, Address Byte, Two Data Bytes and a Stop bit. This sample rate is measured from one Start Bit to the next Start Bit. For continuous conversions (requested by the Master by issuing an acknowledge after a conversion), the maximum sample rate is measured from conversion to conversion or a total of 18 clocks (two data bytes and two Acknowledge bits). Refer to Section 5.2 "Device Addressing", "Device Addressing". EQUATION V DD LSB SIZE = -----------4096 VDD = Supply voltage The output code of the MCP3221 is transmitted serially with MSB first. The format of the code is straight binary. Output Code 1111 1111 1111 1111 1111 1110 (4095) (4094) 0000 0000 0011 (3) 0000 0000 0010 (2) 0000 0000 0001 (1) 0000 0000 0000 (0) .5 LSB 1.5 LSB 2.5 LSB AIN VDD-1.5 LSB VDD-2.5 LSB FIGURE 4-1: Transfer Function. (c) 2006 Microchip Technology Inc. DS21732C-page 13 MCP3221 4.5 Differential Non-Linearity (DNL) 4.8 Gain Error In the ideal A/D converter transfer function, each code has a uniform width. That is, the difference in analog input voltage is constant from one code transition point to the next. Differential nonlinearity (DNL) specifies the deviation of any code in the transfer function from an ideal code width of 1 LSB. The DNL is determined by subtracting the locations of successive code transition points after compensating for any gain and offset errors. A positive DNL implies that a code is longer than the ideal code width, while a negative DNL implies that a code is shorter than the ideal width. The gain error determines the amount of deviation from the ideal slope of the A/D converter transfer function. Before the gain error is determined, the offset error is measured and subtracted from the conversion result. The gain error can then be determined by finding the location of the last code transition and comparing that location to the ideal location. The ideal location of the last code transition is 1.5 LSBs below full-scale or VDD. 4.9 Conversion Current (IDD) 4.6 Integral Non-Linearity (INL) The average amount of current over the time required to perform a 12-bit conversion. Integral nonlinearity (INL) is a result of cumulative DNL errors and specifies how much the overall transfer function deviates from a linear response. The method of measurement used in the MCP3221 A/D converter to determine INL is the "end-point" method. 4.10 Active Bus Current (IDDA) The average amount of current over the time required to monitor the I2C bus. Any current the device consumes while it is not being addressed is referred to as "Active Bus" current. 4.7 Offset Error 4.11 Offset error is defined as a deviation of the code transition points that are present across all output codes. This has the effect of shifting the entire A/D transfer function. The offset error is measured by finding the difference between the actual location of the first code transition and the desired location of the first transition. The ideal location of the first code transition is located at 1/2 LSB above VSS. Standby Current (IDDS) The average amount of current required while no conversion is occurring and while no data is being output (i.e., SCL and SDA lines are quiet). 4.12 I2C Standard Mode Timing I2C specification where the frequency of SCL is 100 kHz. 4.13 I2C Fast Mode Timing I2C specification where the frequency of SCL is 400 kHz. DS21732C-page 14 (c) 2006 Microchip Technology Inc. MCP3221 5.0 5.1 SERIAL COMMUNICATIONS I2C Bus Characteristics The following bus protocol has been defined: * Data transfer may be initiated only when the bus is not busy. * During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a START or STOP condition. Accordingly, the following bus conditions have been defined (refer to Figure 5-1). Each data transfer is initiated with a START condition and terminated with a STOP condition. The number of data bytes transferred between the START and STOP conditions is determined by the master device and is unlimited. 5.1.5 ACKNOWLEDGE Each receiving device, when addressed, is obliged to generate an acknowledge bit after the reception of each byte. The master device must generate an extra clock pulse which is associated with this acknowledge bit. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable-low during the high period of the acknowledge-related clock pulse. Setup and hold times must be taken into account. During reads, a master device must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave (NAK). In this case, the slave (MCP3221) will release the bus to allow the master device to generate the STOP condition. The MCP3221 supports a bidirectional, 2-wire bus and data transmission protocol. The device that sends data onto the bus is the transmitter and the device receiving data is the receiver. The bus has to be controlled by a master device which generates the serial clock (SCL), controls the bus access and generates the START and STOP conditions, while the MCP3221 works as a slave device. Both master and slave devices can operate as either transmitter or receiver, but the master device determines which mode is activated. 5.1.1 BUS NOT BUSY (A) Both data and clock lines remain high. 5.1.2 START DATA TRANSFER (B) A high-to-low transition of the SDA line while the clock (SCL) is high determines a START condition. All commands must be preceded by a START condition. 5.1.3 STOP DATA TRANSFER (C) A low-to-high transition of the SDA line while the clock (SCL) is high determines a STOP condition. All operations must be ended with a STOP condition. 5.1.4 DATA VALID (D) The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the clock signal's high period. The data on the line must be changed during the low period of the clock signal. There is one clock pulse per bit of data. SCL (A) (B) (D) (D) (C) (A) SDA START CONDITION DATA ADDRESS OR ACKNOWLEDGE ALLOWED TO CHANGE VALID STOP CONDITION FIGURE 5-1: Data Transfer Sequence on the Serial Bus. (c) 2006 Microchip Technology Inc. DS21732C-page 15 MCP3221 5.2 Device Addressing 5.3 Executing a Conversion The address byte is the first byte received following the START condition from the master device. The first part of the control byte consists of a 4-bit device code, which is set to 1001 for the MCP3221. The device code is followed by three address bits: A2, A1 and A0. The default address bits are 101. Contact the Microchip factory for additional address bit options. The address bits allow up to eight MCP3221 devices on the same bus and are used to determine which device is accessed. The eighth bit of the slave address determines if the master device wants to read conversion data or write to the MCP3221. When set to a `1', a read operation is selected. When set to a `0', a write operation is selected. There are no writable registers on the MCP3221. Therefore, this bit must be set to a '1' in order to initiate a conversion. The MCP3221 is a slave device that is compatible with the I2C 2-wire serial interface protocol. A hardware connection diagram is shown in Figure 6-2. Communication is initiated by the microcontroller (master device), which sends a START bit followed by the address byte. On completion of the conversion(s) performed by the MCP3221, the microcontroller must send a STOP bit to end communication. The last bit in the device address byte is the R/W bit. When this bit is a logic `1', a conversion will be executed. Setting this bit to logic `0' will also result in an "acknowledge" (ACK) from the MCP3221, with the device then releasing the bus. This can be used for device polling. Refer to Section 6.3 "Device Polling", "Device Polling", for more information. START READ/WRITE SLAVE ADDRESS R/W A SCL This section will describe the details of communicating with the MCP3221 device. Initiating the sample-andhold acquisition, reading the conversion data and executing multiple conversions will be discussed. 5.3.1 INITIATING THE SAMPLE AND HOLD The acquisition and conversion of the input signal begins with the falling edge of the R/W bit of the address byte. At this point, the internal clock initiates the sample, hold and conversion cycle, all of which are internal to the ADC. tACQ + tCONV is initiated here Address Byte SCL 1 2 3 4 5 6 7 8 9 ACK SDA Start Bit 1 0 0 1 A2 A1 A0 R/W Address bits Device bits FIGURE 5-3: Address Byte. Initiating the Conversion, tACQ + tCONV is initiated here Lower Data Byte (n) 17 18 19 20 21 22 23 24 25 26 ACK SDA D8 D7 D6 D5 D4 D3 D2 D2 D0 Device Code Address Bits(1) Note 1: Contact Microchip for additional address bits. FIGURE 5-4: Initiating the Conversion, Continuous Conversions. FIGURE 5-2: Device Addressing. DS21732C-page 16 (c) 2006 Microchip Technology Inc. ACK 1 0 0 1 1 0 1 MCP3221 The input signal will initially be sampled with the first falling edge of the clock following the transmission of a logic-high R/W bit. Additionally, with the rising edge of the SCL, the ADC will transmit an acknowledge bit (ACK = 0). The master must release the data bus during this clock pulse to allow the MCP3221 to pull the line low (refer to Figure 5-3). For consecutive samples, sampling begins on the falling edge of the LSB of the conversion result, which is two bytes long. Refer to Figure 5-6 a for timing diagram. 5.3.2 READING THE CONVERSION DATA Once the MCP3221 acknowledges the address byte, the device will transmit four `0' bits followed by the upper four data bits of the conversion. The master device will then acknowledge this byte with an ACK = Low. With the following 8 clock pulses, the MCP3221 will transmit the lower eight data bits from the conversion. The master then sends an ACK = high, indicating to the MCP3221 that no more data is requested. The master can then send a stop bit to end the transmission. tACQ + tCONV is initiated here 1 SCL S T A R T SDA S 1 0 Address Byte R / W A C K Upper Data Byte A CD K7 Lower Data Byte N A K S T O P P 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 0 1 A 2 A 1 A 0 0 0 0 0 DDD 11 10 9 D 8 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Device bits Address bits FIGURE 5-5: 5.3.3 Executing a Conversion. CONSECUTIVE CONVERSIONS For consecutive samples, sampling begins on the falling edge of the LSB of the conversion result. See Figure 5-6 for timing. tACQ + tCONV is initiated here tACQ + tCONV is initiated here fSAMP = 22.3 ksps (fCLK = 400 kHz) 1 SCL S T A R T SDA S 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Address Byte Upper Data Byte (n) Lower Data Byte (n) 0 0 1 A2 A1 A0 R / W A C K 0 0 0 0 DDD 11 10 9 D 8 A C K D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 A C K 0 Device bits Address bits FIGURE 5-6: Continuous Conversion. (c) 2006 Microchip Technology Inc. DS21732C-page 17 MCP3221 6.0 6.1 APPLICATIONS INFORMATION Driving the Analog Input The MCP3221 has a single-ended analog input (AIN). For proper conversion results, the voltage at the AIN pin must be kept between VSS and VDD. If the converter has no offset error, gain error, INL or DNL errors, and the voltage level of AIN is equal to or less than VSS + 1/2 LSB, the resultant code will be 000h. Additionally, if the voltage at AIN is equal to or greater than VDD - 1.5 LSB, the output code will be FFFh. VDD RSS AIN VT = 0.6V The analog input model is shown in Figure 6-1. In this diagram, the source impedance (RSS) adds to the internal sampling switch (RS) impedance, directly affecting the time required to charge the capacitor (CSAMPLE). Consequently, a larger source impedance increases the offset error, gain error and integral linearity errors of the conversion. Ideally, the impedance of the signal source should be near zero. This is achievable with an operational amplifier, such as the MCP6022, which has a closed-loop output impedance of tens of ohms. Sampling Switch SS RS = 1 k CSAMPLE = DAC capacitance = 20 pF VSS VA CPIN 7 pF VT = 0.6V ILEAKAGE 1 nA Legend VA RSS AIN CPIN VT ILEAKAGE SS RS CSAMPLE = = = = = = = = = signal source source impedance analog input pad analog input pin capacitance threshold voltage leakage current at the pin due to various junctions sampling switch sampling switch resistor sample/hold capacitance FIGURE 6-1: Analog Input Model, AIN. The number of devices connected to the bus is limited only by the maximum bus capacitance of 400 pF. A possible configuration using multiple devices is shown in Figure 6-3. SDA SCL PIC16F876 Microcontroller 6.2 Connecting to the I2C Bus The I2C bus is an open-collector bus, requiring pull-up resistors connected to the SDA and SCL lines. This configuration is shown in Figure 6-2. VDD PICmicro(R) Microcontroller RPU MCP3221 SDA AIN SCL RPU 24LC01 EEPROM Analog Input Signal MCP3221 12-bit ADC TC74 Temperature Sensor RPU is typically: 10 k for fSCL = 100 kHz 2 k for fSCL = 400 kHz FIGURE 6-2: Bus. Pull-up Resistors on I2C FIGURE 6-3: Bus. Multiple Devices on I2CTM DS21732C-page 18 (c) 2006 Microchip Technology Inc. MCP3221 6.3 Device Polling In some instances, it may be necessary to test for MCP3221 presence on the I2C bus without performing a conversion. This operation is described in Figure 6-4. Here we are setting the R/W bit in the address byte to a zero. The MCP3221 will then acknowledge by pulling SDA low during the ACK clock and then release the bus back to the I2C master. A stop or repeated start bit can then be issued from the master and I2C communication can continue. Address Byte SCL SDA 123456789 ACK 100 1 Digital and analog traces should be separated as much as possible on the board, with no traces running underneath the device or the bypass capacitor. Extra precautions should be taken to keep traces with highfrequency signals (such as clock lines) as far as possible from analog traces. Use of an analog ground plane is recommended in order to keep the ground potential the same for all devices on the board. Providing VDD connections to devices in a "star" configuration can also reduce noise by eliminating current return paths and associated errors (Figure 6-6). For more information on layout tips when using the MCP3221 or other ADC devices, refer to AN688, "Layout Tips for 12-Bit A/D Converter Applications". VDD Connection A2 A1A0 0 Start R/W Bit Device bits Address bits Start Bit MCP3221 response FIGURE 6-4: Device Polling. Device 1 Device 4 6.4 6.4.1 Device Power and Layout Considerations POWERING THE MCP3221 Device 2 Device 3 VDD supplies the power to the device as well as the reference voltage. A bypass capacitor value of 0.1 F is recommended. Adding a 10 F capacitor in parallel is recommended to attenuate higher frequency noise present in some systems. VDD VDD 10 F 0.1 F VDD FIGURE 6-6: VDD traces arranged in a `Star' configuration in order to reduce errors caused by current return paths. 6.4.3 USING A REFERENCE FOR SUPPLY AIN SCL SDA RPU RPU To MCP3221 Microcontroller The MCP3221 uses VDD as both power and a reference. In some applications, it may be necessary to use a stable reference to achieve the required accuracy. Figure 6-7 shows an example using the MCP1541 as a 4.096V, 2% reference. VDD 0.1 F FIGURE 6-5: 6.4.2 Powering the MCP3221. VDD SCL MCP3221 SDA RPU When laying out a printed circuit board for use with analog components, care should be taken to reduce noise wherever possible. A bypass capacitor from VDD to ground should always be used with this device and should be placed as close as possible to the device pin. A bypass capacitor value of 0.1 F is recommended. FIGURE 6-7: Stable Power and Reference Configuration. (c) 2006 Microchip Technology Inc. DS21732C-page 19 To Microcontroller LAYOUT CONSIDERATIONS MCP1541 CL 4.096V Reference AIN 1 F VDD MCP3221 7.0 7.1 PACKAGING INFORMATION Package Marking Information 5-Pin SOT-23A (EIAJ SC-74) Device 3 2 1 4 5 Part Number MCP3221A0T-I/OT MCP3221A1T-I/OT MCP3221A2T-I/OT MCP3221A3T-I/OT MCP3221A4T-I/OT MCP3221A5T-I/OT MCP3221A6T-I/OT MCP3221A7T-I/OT MCP3221A0T-E/OT MCP3221A1T-E/OT MCP3221A2T-E/OT MCP3221A3T-E/OT MCP3221A4T-E/OT MCP3221A5T-E/OT MCP3221A6T-E/OT MCP3221A7T-E/OT Address Option 000 001 010 011 100 101 110 111 000 001 010 011 100 101 110 111 SOT-23 EE EH EB EC ED S1 * EF EG GE GH GB GC GD GA * GF GG * Default option. Contact Microchip Factory for other address options. Legend: 1 2 3 4 Part Number code + temperature range Part Number code + temperature range Year and work week Lot ID Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard device marking consists of Microchip part number, year code, week code, and traceability code. DS21732C-page 20 (c) 2006 Microchip Technology Inc. MCP3221 5-Lead Plastic Small Outline Transistor (OT) (SOT23) E E1 p B p1 D n 1 c A A2 Units Dimension Limits Number of Pins Pitch Outside lead pitch (basic) Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom n p p1 A A2 A1 E E1 D L f c B a b L A1 INCHES* MIN NOM 5 .038 .075 .035 .035 .000 .102 .059 .110 .014 0 .004 .014 0 0 .006 .017 5 5 .046 .043 .003 .110 .064 .116 .018 5 .057 .051 .006 .118 .069 .122 .022 10 .008 .020 10 10 0.35 0.90 0.90 0.00 2.60 1.50 2.80 0.35 MAX MIN MILLIMETERS NOM 5 0.95 1.90 1.18 1.10 0.08 2.80 1.63 2.95 0.45 0 0.09 0 0 0.15 0.43 5 5 5 1.45 1.30 0.15 3.00 1.75 3.10 0.55 10 0.20 0.50 10 10 MAX * Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. EIAJ Equivalent: SC-74A Revised 09-12-05 Drawing No. C04-091 (c) 2006 Microchip Technology Inc. DS21732C-page 21 MCP3221 NOTES: DS21732C-page 22 (c) 2006 Microchip Technology Inc. MCP3221 APPENDIX A: REVISION HISTORY Revision C (July 2006) * Section 5.2 Device Address: Changed 4-bit device code to "1001". Changed three address bits to "101". Revision B (May 2003) * Numerous changes throughout document. Revision A (November 2005) * Original Release of this Document. (c) 2006 Microchip Technology Inc. DS21732C-page 23 MCP3221 NOTES: DS21732C-page 24 (c) 2006 Microchip Technology Inc. MCP3221 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device XX Address Options X Temperature Range /XX Package Examples: a) b) c) d) Temperature Range: I = -40C to +85C E = -40C to +125C XX A0 A1 A2 A3 A4 A5 * A6 A7 = = = = = = = = A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 MCP3221A0T-I/OT: MCP3221A1T-I/OT: MCP3221A2T-I/OT: MCP3221A3T-I/OT: MCP3221A4T-I/OT: MCP3221A5T-I/OT: MCP3221A6T-I/OT: MCP3221A7T-I/OT: Device: MCP3221T: 12-Bit 2-Wire Serial A/D Converter (Tape and Reel) e) f) g) h) a) b) c) d) e) f) g) h) Address Options: Industrial, A0 Address, Tape and Reel Industrial, A1 Address, Tape and Reel Industrial, A2 Address, Tape and Reel Industrial, A3 Address, Tape and Reel Industrial, A4 Address, Tape and Reel Industrial, A5 Address, Tape and Reel Industrial, A6 Address, Tape and Reel Industrial, A7 Address, Tape and Reel * Default option. Contact Microchip factory for other address options Package: OT = SOT-23, 5-lead (Tape and Reel) MCP3221A0T-E/OT: Extended, A0 Address, Tape and Reel MCP3221A1T-E/OT: Extended, A1 Address, Tape and Reel MCP3221A2T-E/OT: Extended, A2 Address, Tape and Reel MCP3221A3T-E/OT: Extended, A3 Address, Tape and Reel MCP3221A4T-E/OT: Extended, A4 Address, Tape and Reel MCP3221A5T-E/OT: Extended, A5 Address, Tape and Reel MCP3221A6T-E/OT: Extended, A6 Address, Tape and Reel MCP3221A7T-IE/OT: Extended, A7 Address, Tape and Reel (c) 2006 Microchip Technology Inc. DS21732C-page 25 MCP3221 NOTES: DS21732C-page 26 (c) 2006 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: * * * Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." * * Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2006, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company's quality system processes and procedures are for its PICmicro(R) 8-bit MCUs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. (c) 2006 Microchip Technology Inc. DS21732C-page 27 WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Habour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Atlanta Alpharetta, GA Tel: 770-640-0034 Fax: 770-640-0307 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 San Jose Mountain View, CA Tel: 650-215-1444 Fax: 650-961-0286 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 ASIA/PACIFIC Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8676-6200 Fax: 86-28-8676-6599 China - Fuzhou Tel: 86-591-8750-3506 Fax: 86-591-8750-3521 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Shunde Tel: 86-757-2839-5507 Fax: 86-757-2839-5571 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xian Tel: 86-29-8833-7250 Fax: 86-29-8833-7256 ASIA/PACIFIC India - Bangalore Tel: 91-80-4182-8400 Fax: 91-80-4182-8422 India - New Delhi Tel: 91-11-5160-8631 Fax: 91-11-5160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Gumi Tel: 82-54-473-4301 Fax: 82-54-473-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Penang Tel: 60-4-646-8870 Fax: 60-4-646-5086 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 EUROPE Austria - Wels Tel: 43-7242-2244-3910 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 06/08/06 DS21732C-page 28 (c) 2006 Microchip Technology Inc. |
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